The present invention relates to a semiconductor circuit device which has a first stage logic circuit for receiving an external input signal and a plurality of inverters for forwarding an output from the first stage logic circuit to a following stage and which reaches an active state only when an activating signal applied thereto is active.
FIG. 5 shows in a circuit diagram a prior art semiconductor circuit device of the kind to which the present invention relates and FIG. 6 shows in waveforms a performance of the prior art device shown in FIG. 5.
In the illustrated prior art semiconductor circuit device, a first stage logic circuit consists of an input stage inverter circuit INV.sub.1. The input stage inverter circuit INV.sub.1 comprises a P-channel MOS transistor Q.sub.P (hereinafter referred to as "transistor Q.sub.P ") and an N-channel MOS transistor Q.sub.N (hereinafter referred to as "transistor Q.sub.N "). This first stage inverter circuit INV.sub.1 receives at its input a signal .phi.IN applied to an external terminal TM and outputs its output signal to a node V.sub.1. Inverters INV.sub.2, INV.sub.3 operate as a buffer circuit and output the signal at the node V.sub.1 to nodes V.sub.2, V.sub.3 in a serial order. An input threshold level of the inverter INV.sub.1 in the circuit is determined by the conductance ratio of the transistors Q.sub.P, Q.sub.N which constitute the inverter INV.sub.1 itself but, as shown in FIG. 6, such threshold level fluctuates as a change takes place in a power supply potential V.sub.cc and a ground potential GND in a semiconductor chip.
In the prior art semiconductor circuit device as described above, whereas the input signal externally inputted to the first stage logic circuit is not influenced by a change in the power supply potential V.sub.cc and the ground potential GND within the semiconductor chip, the input threshold level of the first stage logic circuit is influenced by such change and does fluctuate. Thus, a drawback is that, at the time shown by an arrow in FIG. 6, there occur errors in the input level judging operation in the first stage logic circuit by the changes in the power supply potential V.sub.cc and the ground potential GND within the semiconductor chip.